이창혁, Changhyuk Lee, Ph.D.

EDUCATION:

Cornell University, Ithaca, NY, USA
Ph.D. in Electrical and Computer Engineering (August 2014)

Korea University, Seoul, Rep. of Korea
B.S. summa cum laude in Electrical and Computer Engineering (March 2001 – February 2005)

EDUCATION
M.S. Electrical Engineering, Department of Electronics, The National Technical University of Ukraine “Igor Sikorsky Kyiv Polytechnic Institute”, Ukraine (2017)

B.S. Electrical Engineering, Department of Electronics, The National Technical University of Ukraine “Igor Sikorsky Kyiv Polytechnic Institute”, Ukraine (2015)

EDUCATION
B.S. Electronics and Electrical Engineering, Department of Engineering, Dongguk University (2018)

EDUCATION
B.S. Electronic Engineering, Department of EE, Kookmin University (2018)

EDUCATION
Undergraduate, Electrical Engineering, University of Michigan

A 72×60, angle-sensitive single photon avalanche diode (A-SPAD) array for lens-less 3D fluorescence lifetime imaging. An A-SPAD pixel consists of a SPAD to provide precise photon arrival time where a time-resolved operation is utilized to avoid stimulus-induced saturation, and integrated diffraction gratings on top of the SPAD to extract incident angles of the incoming light. The combination enables mapping of fluorescent sources with different lifetimes in 3D space down to micrometer scale. Futhermore, the chip presented herein integrates pixel-level counters to reduce output data-rate and to enable a precise timing control.

An inductively powered, orthogonal current-reuse multi-channel amplifier for power-efficient neural recording. The power rectifier uses the input swing as a self-synchronous charge pump, making it a fully passive, full-wave ladder rectifier.

A CMOS image sensor for efficient capture of polar symmetric imaging targets. The array uses circular photodiodes, arranged in concentric rings to capture, for example, diffraction patterns generated by optically probing a revolving MEMS device. The chip is designed with a vacant, central spot to facilitate the easy single-axis alignment of the probing illumination, target device, and detector. Imaging of high-speed rotation (>1 kfps) is made possible by dividing the array into multiple concentric bands with sectorwise addressing control.

An all digital low-power CMOS edge detection image sensors array. Each pixel contains a voltage-controlled ring oscillator to achieve low power and cost efficient digital only edge detection. While conventional edge detection methods require high computing power as well as large chip area to process intensity maps, this work implements all-digital parallel processing algorithm that detects differences between neighboring pixel pairs on-chip, hence reducing the aforementioned power and cost overheads. In particular, a simple columnshared frequency comparator enables low power operation by eliminating arithmetic computations with large memory requirement. Such simple edge detection algorithm allows the processor area to be less than 16% of the entire image sensor, therefore maximizing the proportion of active optical area.

Although there is much active research on softwaredefined radios (SDRs) with receive (RX) or transmit (TX) functionality, little work has been done on SDR transceivers supporting frequency division duplex (FDD). In this paper, we present a new circuit concept in which a distributed TX circuit cancels the transmitted signal at a reverse RX port through destructive interference while adding signal constructively at a forward TX port. We pair the distributed transmitter with a receiver-tracking PA degeneration technique to suppress the injected noise from TX circuits in the RX band. The system does not require off-chip filters or circulators, but still achieves both SDR flexibility and both FDD and time division duplex function. Measurements from the transceiver implemented in 65-nm CMOS show a frequency tuning range of 0.3–1.6 GHz with TX–RX isolation >23 dB and transmitted power up to 19 dBm.